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Spiders for FPGA Applications.
| 题名： | Spiders for FPGA Applications. |
| 作者： | Allwein, G; Belmonte, C. |
| 摘要： | This is a report on the abstract structure of spiders for applications. A spider is a realtime monitor of Field Programmable Gate Arrays(FPGAs) and Complex Programmable Logic Devices (CPLDs). The FPGAs and CPLDs are assumed to contain applications coded in VHDL.Each spider is associated with specific logic statements expressing conditions in the application code being monitored. Each spider also containsmechanisms for mitigating the effects of an exploit, either malicious, due to an error in design, or due to a hardware fault. Spiders can be writtenin any language provided there is a translator into a language that vendor supplied tools support. Eventually, spiders will be automaticallycompiled from logic statements and mitigation code to produce either VHDL code or ReWire code. ReWire has its own compiler that produceseither VHDL or Verilog code, which would then subsequently be included in the application. |
| 总页数： | 58 pages |
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